1. Field of Invention
The present invention relates to a method of forming a contact in semiconductor device, and more particularly, to a method of forming a borderless contact in semiconductor device which minimizes loss of field oxide when forming a contact hole. This reduces leakage current at an interface between an active area and a field area and prevents further loss of silicon and silicide in the active area by forming a barrier layer on a field oxide layer in order to enhance a process margin of forming the contact hole in the active area due to a reduced design rule and an increased device integration.
2. Discussion of Related Art
In general, trench isolation is achieved by forming a trench between active areas to be separated and by filling the trench with oxide and the like for electrical isolation. Devices such as transistors are then formed in the active area or over the trench.
In a trench isolation method forming a borderless contact on a trench causes some problems. A borderless contact means that a contact is formed on a specific area through an active area and a field area on a semiconductor substrate. One of the problems is that it is hard to keep a trench isolation area intact when forming a contact hole by etching an insulating interlayer.
When forming an ordinary contact hole, there is no field oxide loss from forming a direct contact if a space between a gate and a field oxide is sufficient for the size of the contact hole. In this case, the contact hole lies just on the active area without a portion overlapped with the field oxide.
Actually, when an active layer consists of a silicon junction or salicide such as Co, Ti or the like, there is no field oxide loss because a border between the active area and the field oxide layer is free by an attack from an etchant used to form a contact hole. Thus, no leakage current occurs in the border.
If an active area between a field area and a gate line is smaller than the size of a contact hole, or if the contact hole lies overlaps both a field oxide layer and the active layer, a loss of field oxide overlapped with the contact hole is caused by an overetch in etching an insulating interlayer. In this case, leakage current as well as cell separation failure is brought about by damage to an exposed substrate caused by plasma. Accordingly, a nitride layer for protecting the field oxide layer is deposited on the field oxide layer after a gate line has been formed or a salicide layer has been formed on the active area.
An ordinary contact does not requires an etch-stopping layer from forming a contact hole, but a borderless contact requires an additional nitride layer. Thus, a process of forming a borderless contact needs an extra step of etching the additional nitride layer. In this case, it is essential for a nitride layer etch to employ a high etch selectivity between silicon and salicide(or silicide).
U.S. Pat. No. 5,677,231 (Oct. 14, 1997), U.S. Pat. No. 5,654,589 (Aug. 5, 1997), U.S. Pat. No. 5,759,867 (Jun. 2, 1998) show methods of etching etch-stop layers or a methods of forming a protective layer over a field oxide layer. They show a method of carrying out a secondary etch after first dry etching an oxide layer when forming a contact hole, and a method of carrying out chemical-mechanical polishing of an extra layer for protecting silicon in an active area before filling up a trench.
FIG. 1A to FIG. 1E are cross-sectional views illustrating formation of a contact in a semiconductor device according to the related art.
Referring to FIG. 1A, an oxide layer 11 in a trench is formed after a predetermined portion of a silicon semiconductor substrate 10 of is removed by photolithography to form the trench. In this case, the trench is filled by depositing silicon oxide on the silicon substrate 10 including the trench and then, etching back etching back the silicon oxide. However, a shallow groove is formed on an upper edge of the oxide layer 11 in the trench due to a physical characteristic of an overetch.
A polycrystalline silicon layer doped with impurity ions is formed to form a gate, after forming an oxide layer on the exposed substrate 10. A silicon nitride layer for forming a capping insulating layer 14 on the polycrystalline layer.
A gate pattern 12-14 is defined by patterning the silicon nitride layer the polycrystalline silicon layer the gate oxide layer using a dry etch thereby obtaining gate oxide layer 12, gate 13, and capping insulating layer 14. A sidewall spacer 15 of silicon oxide is formed by etching back a silicon oxide layer having been deposited on the whole substrate 10. Including the gate pattern, an lightly doped buried layer for a lightly doped drain(hereinafter abbreviated LDD) junction, not shown in the drawing, is formed around a lower edge of the gate 13 on the substrate 10 by lightly doping the substrate with impurity ions lightly.
After the forming the sidewall spacer 15, a source/drain junction 16 is formed by a heavy ion implantation. A salicide layer 17 for reducing electrical resistance is formed on the exposed source/drain junction 16 to complete a MOS transistor.
Referring to FIG. 1B, a nitride layer 18 is formed on a whole surface of the substrate 10 including the salicide layer 17, the transistor, and the field oxide layer 11. The nitride layer 18 has a very high etch selectivity relative to oxide, silicon, and salicide when forming a borderless contact. Thus, the nitride layer becomes a barrier layer in forming a contact hole in two steps.
Referring to FIG. 1C, an insulating oxide interlayer 19 for protection and planarization is thickly formed on the nitride layer 18. The insulating interlayer 19 is coated with photoresist. A photoresist pattern 20 is then formed exposing a portion of the insulating interlayer 19 over a borderless contact to defined a borderless contact area.
Referring to FIG. 1D, a portion of the nitride layer 18 is exposed by dry etching a portion of the insulating interlayer 19 not covered with the photoresist pattern 20. The dry etch is carried out using a C.sub.2 F.sub.6 etchant, using the photoresist pattern 20 as an etch mask. The photoresist pattern is then removed. Referring to FIG. 1E, a contact hole exposing both the salicide layer 17 and the field oxide layer 11 is formed by dry etching an exposed portion of the nitride layer 18. In this case, C.sub.2 F.sub.6 and O.sub.2 are used as etchants. The resulting contact hole is a so-called borderless contact hole because the contact hole is formed through the field oxide layer and the salicide layer 17.
Unfortunately, the method of forming a contact in semiconductor device according to the related art suffer from, for example, failure of cell isolation and the loss of salicide and field oxide layers of which portions are etched away in etching a nitride layer. Therefore, leakage current is caused by the damaged silicon overetched by plasma.